1. Field of the Invention
This invention relates to SRAM memory devices and more particularly to improved load resistors therefor.
2. Description of Related Art
U.S. Pat. No. 5,200,356 of Tanaka for "Method of Forming a Static Random Access Memory Device" and U.S. Pat. No. 4,950,620 of Harrington for "Process for Making Integrated Circuit with Doped Silicon Dioxide Load Elements" show SRAM devices with load resistors formed by ion implantation of impurities in a silicon dioxide film.
U.S. Pat. No. 5,126,279 of Roberts for "Single Polysilicon Cross-Coupled Resistor, Six Transistor SRAM Cell Design Technique" shows an SRAM using polysilicon resistors.
U.S. Pat. No. 5,266,156 of Nsar for "Methods of Forming a Local Interconnect and a High Resistor Polysilicon Load by Reacting Cobalt with Polysilicon" and U.S. Pat. No. 5,268,325 of Spinner et al for "Method for Fabricating a Polycrystalline Silicon Resistive Load Element in an Integrated Circuit" show methods for making polysilicon load resistors.
FIG. 2 is a sectional view of a fragment of a prior art SRAM (Static Random Access Memory) device 9 with a substrate 10 composed of silicon. The device includes a FOX (field oxide) region 11 upon which a polysilicon 1 gates 12 and 16 are formed with silicon dioxide spacers 13 on either side. Polysilicon 1 gate 16 extends across the edge of the FOX region 11 in direct contact with the surface of the silicon substrate 10. Above that structure is formed an interpolysilicon structure 14 with an opening 17 therethrough above the gate 16. Next, a blanket layer 15 of undoped polysilicon 2 resistor material is formed over the preceding layers. Layer 15 in stacked contact through opening 17 with polysilicon 1 gate 16.
Prior art polysilicon ion implanted resistors have had a length of from about 2 .mu.m to about 6 .mu.m with a width of from 0.5 .mu.m to 1.0 .mu.m depending on the design rule or technology. For example, the resistor can be 2.6 .mu.m long and 0.6 .mu.m wide. Outside the masked area there is heavily doped polysilicon. The 2 .mu.m to 4 .mu.m length is provided to insure that there is enough of an undoped region for a high resistance value.
The problem with conventional polysilicon load resistors is that they suffer large resistance variations and high temperature coefficients.